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15 
The entire logic of the Bx-272 is implemented 
using monolithic integrated circuits; the most obvious 
result of this is that the CPU logic occupies a volume 
of approximately one-half of a cubic foot. Of more 
importance than small size, however, is the fact that 
the economy inherent in the use of integrated circuits 
greatly influenced the formulation of the instruction 
repertoire of the computer. It was possible to incor- 
porate many desirable functions at a very low relative 
cost. 
Table!l Representative Bx-272 Instructions 
Execution Time 
Type of Operation Hsec Remarks 
  
Either Accumulator 
Store, Load, Add, 
Subtract 1.250 Single-Precision 
Clear, Add/Subt. 
Constant 0.625 Immediate Value 
Rotate, Shift 0.625 * 0.175 n Logical or arithmetic 
Imcrement and Skip 0.725 Skip is conditional on 
sign of result 
Coupled Accumulators 
Store, Load, Add, 
Subtract 1.875 Double-Precision 
Multiplication 4.050 36-bit product 
Division 4.650 18-bit quotient 
18-bit remainder 
First Accumulator 
Compare, AND, OR 1.250 With memory operand 
Exchange 1.550 With memory operand 
Compare, Exchange 0.625 With second accumulator 
Input-Output 0.875 With peripheral device 
Index Registers 1, 2 
Load, Store 1.250 With memory operand 
Clear, Add/Subt. 
Constant 0.625 Immediate value 
Increment and Skip 0.725 Skip is conditional on 
sign of result 
Program Counter and Memory 
Jump (Unconditional) 0.625 With address 
modification 
Jump and Mark 1.250 Subroutine call 
Increment Memory 
and Skip 1.350 Skip is conditional on 
sign of result 
Remote Execute 0.625 Execute one instruction 
out of sequence 
Three-Register Instructions 
Add, Subtract, Compare 
AND, OR 0.625 Between all registers, 
including program counter 
and console switches 
Clear, Add/Subt. 
Constant 0.625 Immediate value 
16 
  
SE 
Figure 1 Laboratory Model Bx-272 Computer 
Important factors in developing the computer 
organization were the requirement to provide a pre- 
cision of 32 bits in most calculations and the ability 
to execute a control program in a nearly minimum 
number of memory cycles. To evaluate the efficiency 
of different instruction-sets and machine organiza- 
tions, a number of structures were postulated and 
sample programs were written to test their effective- 
ness. As a result of this evaluation, the basic word 
length of the computer was established as 16 to 18 
bits, and special features were included in the basic 
organization to permit rapid, double-precision arith- 
metic operations. 
Analysis of additional sample programs showed 
that an 18-bit instruction word permitted consider- 
ably more programming efficiency than a 16-bit in- 
struction. The 18-bit instruction permits additional 
flexibility in specifying operations, selection of work- 
ing registers, and memory addressing. These capabili- 
ties result in a 15 to 20 percent decrease in memory 
requirements for a typical program, along with a 
comparable decrease in program execution time. 
As a result of the above evaluation, the computer 
is organized around an 18-bit parallel adder, com- 
municating with flip-flop registers and core memory 
by means of a three-bus system. Buses A and B bring 
the augend and addend inputs from the various regis- 
ters or memory to the adder, while bus S transmits 
the sum output from the adder back to the registers 
or memory. The basic features of the organization are 
shown in Figure 2. 
KAMM, FOLAND, VAN ANDEL, BEHR, AND CHILDS