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8. CONCLUSIONS
The structure of the WAAC- camera has not any restriction on the data rate and solve the scientific tasks of full geometric
resolution. The concept of the camera is based on experiences of other cameras and scanner experiments. The camera is based
on the camera concept which has the possibility to verify algorithms, sensors, processors or architecture for the on- line
imaging process.
The standard differential wide SCSI Il interface is a good compromise concerning of the data rate, cable length and the
opportunity of realization. The advantage of this interface is the capability for the camera control by means of different
computers. The other side is the possibility of the connection with intelligent disk arrays or hard disks.
The camera electronic accomplishes all science tasks. The electronic include the on- line control of the PRNU, DSNU and
compression. Via commands the electronic can generate 11Bit raw data, 8Bit normalised data or JPEG data. The main
advantage of the concept is the capability for testing new processing boards, new sensors or new camera heads. A FPGA
generates the clocks, which can easily be adapted to other sensors or camera heads. The FEE is also controlled by the FPGA
and can also be adapted to test condition of other sensors.
For the first flight in the April of 1995 the camera software has been written for the functional test of the WAAC- application.
But in future we will include the real time kernel for the on- line image processing. It will be the next step in the direction
for a good test facility of the image processing or correction algorithms.
The camera trigger in- and outputs represent the potential of multisensor experiments and of on- line imaging process. For the
on- line imaging process the camera uses the capability of bidirectional transmission of the differential wide SCSI II interface.
9. REFERENCES
(1) Andreas Eckardt, Wide- Angle Airborne Camera (WAAC) OEEPE Workshop digital cameras , IGN
Paris, 28-29.9.1994
(2) Bild & Ton 45 (1993) 9/10 Special issue to WAOSS
(3) WAOCC Feasibility Study F1, DLR Berlin 1993
(4) Joint Photographic Experts Group (JPEG), ISO/IEC, JTC1/SC2/WG8, CCIT, SGVIII, JPEG Technical
Specification Revision 5, Dec 1989
(5) Virtuosos The Virtual Single Processor Programming System Intelligent System International (ISI) Belgium 3/1/1994
10. LIST OF ABBREVIATIONS AND SYMBOLS
CCD : Charge Coupled Devices
DCE : Data Compression Electronic
DCT : Discrete Cosine Transformation
DSNU : Dark Signal Non Uniformity
DSP : Digital Signal Processor
FEE : Eront End Electronic
FIFO : First In First Out memory
FPGA : Field Programmable Gate Arrays
FPM : Focal Plate Module
FOV : Field Of View
GPS : Global Positioning System
HD * Hard Disk
HKD : House Keeping Data
HSYNC : Horizontal Synchronisation
IFOV : |nstantaneous Field Of View
JPEG : Joint Photography Experts Group
PRNU : Photo Response Non Uniformity
RAID : Redundancy Array Independent Disk
SDH : Synchrony Digital Hierarchy
SCSI : Small Computer System Interface
VSYNC : Vertical Synchronisation
IAPRS, Vol.30, Part 5W1, ISPRS Intercommission Workshop "From Pixels to Sequences", Zurich, March 22-24 1995