On each chip, twelve pipeline elements have been fitted. The 
maximum clock speed, which represents also the data throughput upper 
limit in samples per second, has been specified at 5 MHz. This 
results in a performance per IC of 120 MOPS. 
3.2. Processor rack layout 
The range compressor processes complex data. Since a convolution 
merely consists of multiplications and additions, its complex 
counterpart can be composed of four real convolutions, the results of 
which have to be pairwise added and subtracted to obtain the imagina- 
ry and the real part of the complex result. This is schematically 
shown in fig. 3. 
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
Coef. Coef. 
real  imagin. 
é e 
Convolver 1 
> 
| Result 
—— * real 
Subtract p 
— = 
| Convolver 2 
dis 
Data es 
real Convolver 3 Result 
Data | imaging 
ad — + a |__imagin. 
Convolver 4 
  
  
  
  
  
Fig. 3. Complex convolution composed of 4 real convolutions. 
The processor frame is in accordance with this divided in four 
similar blocks. (see fig. 4), each of which contains 7  Euro-size 
PCB's. Input data and/or coefficients are distributed over the Input 
Boards, which precede the real pipelines. From there on, the input 
data are wired via a Backplane to five cascaded Pipeline Boards, 
which themselves contain 12 cascaded gate array chips or 144 real 
convolution pipeline cells. On the Pipeline Boards, the data are 
broadcast to each IC. Thus, one processor pipeline implements a 720- 
point real convolution. 
When kernel coefficients are sent to the Input Boards, they are gated 
to the input port of the first pipeline stage, which is normally 
preset to zero. 
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