4.3 Multiprocessor System ('Type 3')
General Multiprocessor architectures for SAR processing have been reviewed
by Guignard and Jones (1983). The term 'Multiprocessor System' used here is
restricted to the configuration: supervisor/controller system (in most cases
a minicomputer) organizing several or many dedicated processor systems,
structured within a network. 1 War
The 'NEDIPS SAR Processor' developed by NEC (Ito, 1982) is somewhere in
between a 'type 2' and 'type 3' processor. A host computer controls a Tem-
plate Image Processor (TIP), a high speed memory and disks. The TIP's contain
operational units on a circular pipeline reaching a computational perform-
ance of 48 MFLOPS and have to be seen as 'data flow' system. J
The implementation of the RC/AC Algorithm in the frequency domain is already
capable of processing SEASAT full swath images in 4 hours. The projected per-
formance of a NEDIPS with several enhanced TIP's working in. parallel or in
sequence should allow to process a full swath image in less than 10 minutes.
Host
computer I/O data
ber perenne te pie eo el of int = tn fe Sele ES
| |
| Control — ;
| unit NN |
| T tj |
| | en |
| | |
| |
| ud Mihi rin ! lus Memory |] Disk
| | S i | Linterface controller
; i | p |
| Operational Addressor | ! |! —
| unit unit ^ ! | High speed
; || memory
VASEN RR wr se mm See eum zi ELI IL ie mae ee oar m E
TIP External memory subsystem
Figure 2. NEC SAR Processor using NEDIPS
1 ; 1 ;
The NDRE Multiprocessor! (Norsk Data, 1982) is a network of data buses,
supervisor buses for control, signal processors, memories and disks cont-
rolled by a minicomputer as control processor. With a MARS 432 from Numerix
as signal processor, different configurations were analysed that should be
capable of processing an ERS-1 frame in 8 to 30 minutes. The algorithm used
is the well known RC/AC mapped on a rather complex, but fully programmable
PTNPUT |
| oevice |
ae)
RU {|
| | | |
| | | xe: | [rsen | | sse | svo 2 | [lod
jun
Ul à ue | ] TT bas
( rro
SUPERVISOR
(EG. NO. '00
MINICOMPUTER )
PROCESSING |
LINE 1
+ > à A à
La ; | [o | | e] | «|
| T
! 1
+ des 23-4 d +
— } BUSES
[rusas] |Husc-as | | svor s |
MNT ac ci
à land à + J
;
PROCESSING |
LINE 2 |
|
{
i
à d:
| svo 5
[
PROCESSING |
UNE |
{
MouTRUT 1
SVOP - SPEEDY VECTOR-ORIENTED PROCESSOR | sevice |
HUSK-R -STORAGE DEVICE BASED UPON OYNAMIC RAM
Figure 3. NDRE Multiprocessor
206
