ws 
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hardware structure which is based on an earlier developed general concept, 
called 'Martinus'. A specific high level programming language HOLM has been 
created and will support user's system application. 
Two further 'type 3' configurations are under planning in Japan and ltaly. 
Details are not yet available. 
4.4 Hardware Implementations ('Type 4') 
The 5 'type 4' configurations in Table 1 are strongly hardware oriented and 
designed to generate images at Real Time or Near Real Time rates. 
The three processors for airborne SAR sensors are special hardware devices 
with Range and Azimuth Compression performed in time domain. Two realtime 
processors - developed by MDA - are used onboard for quick look and naviga- 
tion support for the CV580 X-Band SAR (Bennett, 1979) and the IRIS C-Band SAR 
(Bennett, 1983). . The |. Marconi. processor. is a8 - groundbased quick. lock 
processor. Two processors are operational, one is nearing its completion 
(IRIS). None of these processors is capable of processing satellite SAR 
data. 
In addition there is one system under development for Near Real Time process- 
ing of satellite SAR sensors. The 'ESA/ESTEC SAR Processor and Test Facility 
(Breadboard)' wich was developed by MDA/Dornier (Okkes, 1983) is depicted in 
Figure 4. It is a system that demonstrated already Near Real Time processing 
capability for the linear range migration correction and the azimuth com- 
pression task of 1/5 subswath assuming nominal ERS-1 parameters. This 
Breadboard is a microprocessor controlled pipeline of Programmable Signal 
Processing Elements (PSPE) and a corner turn memory. It is the only implemen- 
tation that uses the 'Spectral Analysis' algorithm which restricts the 
processor more or less to multilook processing of C/X-Band satellite SAR sen- 
sors. Based on this design a Fast Delivery Processor and a Quick Look 
Processor with reduced resolution were projected for the ERS-1 C-Band SAR 
with throughput estimates of 1/20 and 1/6 of real time respectively. 
OPERATOR |l 
  
  
DIGITAL TEST = DATA FLOW 
SUBSYSTEM 
2 
  
  
  
  
i = + seen 4 up m ER Bern 
  
i 
HD DOPPLER CENTROID FD PIPELINE MASTER = AUTO dq 
{A ESTIMATOR CONTROL UNIT FOCUS ET 
bo ES A ml qe S iuum 
FE SE 
RANGE PROCESS | 
CONTROL UNIT 
  
  
  
  
  
  
  
  
AZIMUTH PROCESS 
CONTROL UNIT 
    
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
| | 
INPUT i IA RANGE CELL REFERENCE E— 1 CORNER  E—HAZIMUTH ter] TE 3 
CODE on] | MIGRATION {A {FUNCTION TURN COMPRESS.] ii LL pDSK 
(n BUEFER =i CORRECTIONT™P] MULTIPLY = MEMORY =H LOOK SUMM. BM Lares 
INPUT = Di 
| | nr wma pedegdoon - rs © 
. .SAR PROCESSOR... 
Figure 4.  ESA/ESTEC SAR Processor and Test Facility 
Áccording to a private communication by Curlander, JPL is planning to develop 
an 'Advanced Digital SAR-Processor ADSP' on new hardware technology to over- 
come the demanding processing problem for the SIR-C sensor in 1987.