Add- 
Subtract 
Control Parallel Adder 
  
  
Bus S 
  
  
  
  
  
  
  
  
Normal Input- 
Bus Output Bus 
  
First Accumulator 
  
Direct 
| Data Bus 
  
  
Second Accumulator and 
Multiplier- Quotient Register 
  
  
  
  
Index Register 1 
BEI 
  
Index Register 2 
  
  
Adder Trace 
Register 
  
Iiis 
| Shift Counter 
  
  
Program Counter 
LET 
  
«a. 
<< 
m 
au 
  
Console Switches 
1s 
  
  
Operand Address Register 
Instruction Register | 
  
  
  
  
  
I 
  
  
  
  
  
  
  
  
  
  
  
  
  
Address 
Data Core Memory (0.625 usecFull Cycle) -— 
d d 8,192 18- Bit Words, Expandable to Data 
32,768 18-Bit Words 
CUTS Direct Memory Access (DMA) Channel 
Data Input - 
Output Bus 
Figure 2 Block Diagram of Central Processor 
The remainder of this section describes the func- 
tions of computer instructions in detail, primarily for 
the benefit of computer designers and programmers. 
Figure 3 shows the data and instruction formats 
which are used for specific types of operations. 
Logical and arithmetic operations have been pro- 
vided which add, subtract, and AND and OR the 
contents, or in some cases, complements of the con- 
tents, of the hardware registers. These operations, 
referred to as three-register instructions, operate not 
only on the accumulators and index registers, but on 
a variety of register combinations. They include three 
address fields that specify which of the operand- 
sources on the A and B buses are to be used, and to 
which destination the S bus is to transmit the result. 
Specifically, field A can select either accumulator, 
either index register, the program counter, or no 
register (zero). Field B can select either the first ac- 
cumulator, the combined trace register-shift counter, 
the shift counter alone, the 18 console switches, or 
no register (zero). Field S is capable of directing the 
results of an operation to either or both accumula- 
tors, either index register, the shift counter, the pro- 
DESIGN OF BX-272 COMPUTER 
gram counter, or no register. 
Particularly useful results of the three-bus struc- 
ture are the clear-register instructions (fields A and B 
both select no register), the nondestructive subtract 
or compare-register instructions (field S selects no 
register), the exchange accumulators instruction (field 
A selects the second accumulator while field B selects 
the direct bus from the first to the second accumula- 
tor, with no register specified for bus B), and the 
program-control jump (field S selects the program 
counter). 
Immediate-value instructions are provided for all 
registers; the *immediate value" is provided by insert- 
ing a number in what are normally the A and B fields. 
Thus a constant ranging in value from 0 to 63 may be 
treated as the contents of a register (though it is 
actually contained in the instruction word) for a 
three-register-type arithmetic operation. Similarly, it 
is possible to skip, in either a positive or negative 
direction, a number of instructions ranging from O to 
63, pending the outcome of a particular arithmetic 
test or as the result of incrementing a register. This is 
particularly valuable for indexed operations. 
1 Bit Sign 
Magnitude 
ein ern EEE ETT ry EEE 
Numa [4 ———— — — — 35 Bits Double Precision —— 
EL EE I LLLI i1. eoe 
17 Bits Single 
Precision 
  
ig 
  
J Address Modification Field 
TTTTTTVTTTTWenen T TYM11 Bits for First 2048 Word 
Memor ords, 
Op Code ANTO | 9 Bits for 512 Words of 
LLL LEE LL EE Active Sector 
= or4 
Bits 
  
Memory Reference 
Instructions 
  
  
  
I-e- 5 Bits Ij——1 1 or 9 Bits ——» 
J Address Modification Field 
  
Ga 7) A TR EL CLL EL PLL LE 
Memory Address 
for 32,768 Words 
lA EL ed 
Indirect Memory 
Address 
LA 
  
  
Li 
3 : 
4———— — rM 
a " 15 Bits 
Output Input Input <e—— Register Selection 
ITTUEIEEPCCETITEEDITA Fields 
Op Code S B A 
LL LL LLLI LI i LA 
  
Three- Register 
Instructions 
  
  
  
  
  
  
l 
i 3 3 3 
EB rini 
1 Bit Add-Subtract Control z Register Selection Field 
  
  
  
  
  
  
  
  
  
  
Immedi Val Fr Lrg ET TT Mn 
mmediate- Value onstan 
Instructions Op Code 0 to 63 
brig Ll LLLA 
; 3 ; 
a 9 Bits "aid re— 6 Bits —9 
4 Bit Function Selector Field 
Shift and FTTTTTTTTT USA f 
Conditional Op Code Constant 
Sip WLR 
Instructions A _ i 
I ——— —— 12 Bits re 6 Bits | 
  
  
  
12 Bit Function Selector Field 
Transfer Clock 
Selector Field 
  
Input-Qutput (1/0) | 1m oL. 
nput- Output | 
Instructions Op Code 
Lib LL LL LU 
A Es i] 
  
  
  
  
  
Figure 3 Word Formats 
17 
—S 
conte 
and 
mem 
ters, 
fied : 
perm 
the t 
videc 
mult 
catio 
prod 
time 
prod 
MICTr( 
Si 
divis: 
COTTE 
latio 
num 
accu 
oper 
The 
men 
whic 
norn 
form 
oper 
stor: 
over 
regis 
whe 
prof 
lowe 
COIT 
tech 
of t 
fron 
the 
begi 
rupi 
at t 
prof 
mul 
spec 
shif 
It i 
stru 
faci 
floa 
18