these buffers and the first accumulator when the 
particular interface indicates its “Ready” status by 
means described below. The result of this is that, in 
effect, simultaneous device operation becomes pos- 
sible. 
The configuration of an input-output instruction is 
shown in Figure 3. Bits 4 through 15 define the de- 
vice and type of function which is desired. Bits 1, 2, 
and 3 are used to select three different timing pulses 
which cause the desired action to occur. Nearly 2,000 
meaningful I/O instructions can be constructed by 
means of this design. 
Several different actions can be effected by means 
of one I/O instruction if desired. Furthermore, the 
action caused by one timing pulse can be determined 
by the result of a test which was made by an earlier 
pulse in the same 0.875-microsecond cycle. An ex- 
ample is the paper-tape reader instruction denoted by 
the octal word 720133. This instruction gates on two 
timing pulses. The first pulse tests whether the reader 
has transferred a tape character into the reader buf- 
fer. If so, the second pulse transfers the character into 
the first accumulator, notifies the computer of the 
parity of the character, and initiates tape motion to 
acquire the next character. 
All three of the timing pulses can be employed to 
perform tests and transmit status information back to 
the computer. A unique feature of the logic which 
results from this capability is that these tests can 
modify the memory location from which the next 
program instruction is taken. Thus, up to eight dis- 
tinct interface conditions can be determined in a 
single I/O instruction cycle. This feature avoids the 
need for time-consuming status-checking subroutines. 
To minimize programmed monitoring and pri- 
ority-checking for relatively slow external devices, 
and to provide for rapid response to certain arith- 
metic and external-condition signals, a multilevel, 
priority interrupt system has been devised. Presently 
implemented in three hardware-determined priority 
levels, the interrupt system can begin to respond to 
an interrupt request within a maximum of 5.5 micro- 
seconds. The total latency period, or time required to 
determine which device caused the interrupt and 
prepare the computer to service it, is a function of 
the number of devices associated with a given inter- 
rupt level. For 17 devices on a level, the maximum 
latency period is 13 microseconds, measured from the 
start of the interrupt request to the start of servicing 
of the lowest priority device. 
Level three, the lowest hardware priority level, is 
used by most peripheral equipment. Level two, which 
can interrupt a level-three interrupt already in pro- 
gress, is presently reserved for the real-time clock. 
Level one, capable of interrupting either level two or 
DESIGN OF BX-272 COMPUTER 
three, handles the power-down condition and the 
divide-check and overflow signals from the arithmetic 
unit. The assignment of devices to any particular 
interrupt level is left to the discretion of the system 
designer. 
A crystal-controlled, real-time clock has been pro- 
vided as a standard part of the system. The oscillator 
frequency is 100 KHz and its output is counted down 
to the desired interrupt rate. The oscillator may be 
turned on or off by means of an I/O command; if left 
on, its interrupt may also be inhibited as needed by 
the systems program. 
A single direct-memory-access channel capable of 
accepting one device is provided with the computer. 
This may be expanded to four channels, each capable 
of accepting eight devices. A hardware priority is 
established between channels and devices within a 
given channel in this case. The expanded system 
exhibits a maximum latency (time between DMA 
request and start of service) of 0.625 microsecond 
and a transfer rate of 1.6 MHz. 
A wide range of peripheral equipment is available 
for the Bx-272. Standard equipment consists of a 
300-character-per-second, bidirectional, paper-tape 
reader; a 50-character-per-second tape punch; and a 
Model 33 Teletype unit. Options include a 40-char- 
acter-per-second data printer, a variety of card readers 
and punches, and multiplexed D/A and A/D con- 
verters. The computer can also be readily interfaced 
with magnetic-tape handlers, disc or drum memories, 
cathode-ray displays, and other digital or analog 
peripheral equipment. 
CIRCUITS 
The logic of the Bx-272 is designed so as to make 
optimum use of core memories having cycle times as 
low as 500 nanoseconds. This capability became eco- 
nomically feasible with the introduction of modern 
monolithic integrated circuits. Of the many inte- 
grated circuit families capable of functioning at 
the required speeds, transistor-transistor logic (TTL) 
was chosen for several reasons. Paramount among 
these are TTL's high noise immunity, its capability of 
operation from a single power-supply voltage, and its 
ability to re-establish logic levels at each level of 
gating. The circuitry chosen exhibits typical propaga- 
tion delays of 6 nanoseconds per gate. 
The basic element of TTL circuitry is a positive 
NAND gate. Its name, transistor-transistor logic, is 
derived from the fact that a multiple-emitter transis- 
tor is used in the input stage. The output stage con- 
sists of two transistors connected in a totem-pole 
configuration. This circuit arrangement provides a 
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