Use of this class of computer in cost effective video based photogrammetric 
systems may not be as far into the future as one might believe, considering 
the track record of electronics to deliver beyond expectations. Photogram- 
metric image systems require prodigious amounts of memory, and that too is 
coming.  Cray-2 for example has 2,048 Mbytes of real memory. The National 
Bureau of Standards has developed a set of benchmark programs for comparing 
the performance of various supercomputer and parallel architectures which 
will be distributed in the second half of 1986. When these are run, some 
adjustment of the figures in Table 1 may be expected. 
4.2 Coprocessors; Parallelism 
The NEC 1280x970 pixel imager for HDTV mentioned earlier has a 48.2 MHz 
charge transfer system, capable of filling a megabyte video memory in 1/30 
sec. The onslaught of such a data input rate, and its impact on image 
processors, will be a difficult challenge. Fortunately, digital signal 
processing lends itself to being broken into compartments that can run on 
separate processors in parallel. Some research efforts visualize one 
processor for each image pixel in a sub array of the imager, Davis, 1984. 
Supercomputer design incorporates various degrees of parallelism. The Intel 
model, Table 1, for example, is based on a 64 node Hypercube architecture 
(California Institute of Technology) where each processor is connected to 
every other processor. 
Real-time image processing is required in electronic image transfer in 
photogrammetric systems which are operator based, hence involve visual 
communication, (i.e. video based Anaplot). Although the stated goal is to 
support this type of operation with 1000x1000 pixel imagery, such imagers, 
and cost-effective processors capable of supporting such imagers, are not 
yet commercially available. Today's "off the shelf" reality is shown in 
Fig. 2: solid state imagers 604H x576V (VSP Labs) and lower, Fig. 2a; slow 
scan imagers of large format having a 4096 linear array, Fig. 2b; and board, 
chip and system level image processor products, Figs. 2c,:/d s and. ie 
respectively. 
Image processor choice depends upon whether algorithms can be specified 
in advance, and also cost sensitivity. Complete real-time systems, Fig. le, 
are general purpose computers with coprocessors and usually offer good 
software support for further development, El-Hakim, 1986. 
Digital signal processing (DSP) chips may either be special purpose or 
general purpose. The TMS320 series (Texas Instruments) is an example of the 
latter type, with its array multiplier, Harvard architecture and reduced 
instruction sets, McDonough, 1982, Allen, 1985. So successful has it been, 
it is now found in over 2000 products including an image coprocessor for the 
IBM-PC, Pawle, 1984. Their growing performance (including floating point) 
in time may replace today's image processing modules containing specialized 
components, especially if paralleled. 
Most speed and flexibility is gained by a processor product family which 
is open architecture in concept. Choice can be made of a host computer (PC 
or other) used to orchestrate a number of specialized parallel coprocessors 
having the functions required to achieve real-time image processing design 
goals. Fig. 2e, El-Hakim, 1986, is a complete system consisting of a 
multiple board set, however its expansion may require factory retrofit. 
Fig. 2c, the board level option, permits choice of functions in an open 
architecture, but software support is weaker. The trend will be towards 
expandable systems with easily integrated software. 
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