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Fig. 
2(a) CCD cameras. The one on the left is an early 100x100 pixel chip 
mounted behind the separate lens while the center one is a more 
modern 100x100 unit. The camera on the right, 380x488 pixels, is 
typical of recent TV compatible units. 
(b) A 4096 linear CCD array mounted behind the lens is swept mechani- 
cally to form a 4096x4096 pixel image in approximately 2 min. 
Image processors: (c) board level 
(d) chip level 
(e) system level 
An example of an existing board level family for real-time image pro- 
cessing is, (Siegal, 1985): 
general purpose arithmetic processor, 
3x3 convolution filter (143 million arithmetic operations per second), 
A/D, D/A conversion; framestore, 
histogram and feature list extraction, 
nonlinear pixel comparison (129 mill {on 8-bit comparisons per second), 
sub pixel multirate sampling and nt _order warping. 
These modules are designed to support either 380x500 or 500x500 pixel video 
inputs. Many of the solid state TV cameras to date have had pixel arrays 
near 
400Hx500V in size, whereas frame memories and CRT controllers have been 
designed around a 512Hx512V format. Processing speed is proportional to 
total pixel count, therefore only the net data frame required, whatever its 
size, should propagate through the processor. 
93