R & D effort to be distributed in a nine month period. The of- 
ficial starting time has been February lst 1986. The specifi- 
cation study period has been split in two slices, namely; 
first three months for the system design study, and the re- 
maining six months for the specification definition. An Advi- 
sory Technical Committee (ATC), formed of a representative 
of each Partner, has the technical responsibility of the  Spe- 
cification Study. It conducts the technical work during the 
first three months and monitors the work undertaken in the 
remaining six months. Four working groups (WG) accomplish 
specialized research during the majority of the specification 
study period, they are: (WGl) real time,  (WG2)  KBS, .(WG3) 
computer technology, and (WG4) simulation-application. 
The real-time WG addresses the problem of SAR processing 
for pixel extraction. Conventional convolution algorithms (e.g, 
FFT) are assessed in terms of performance and computational 
complexity (in view of real time application) and compared 
with a new convolution algorithm based on polyphase filtering 
concept (see Sect. 4.4.1). 
The KBS WG defines the low and high level image processing 
algorithms for the on-line and off-line processing steps re- 
spectively (see Sect. 4.4.2). Image segmentation is of primary 
concern to low level processing. High level processing is con- 
cerned with scene interpretation, detection of nonstationary 
and nonhomogeneous situations and data base updating. Another 
item addressed by KBS WG is the conception of switching proce- 
dures to commute among lst and 2nd looks. 
The computer technology WG addresses the problem of  iden- 
tifying suitable devices and computing architectures for the 
implementation of convolution algorithms for pixel extraction 
and on-line/off-line image processing algorithms. The driving 
factors in the selection of device/architecture are the pro- 
cessing speed, the adaptability to different processing and 
operation modes and the suitability to fault-tolerant design. 
Concerning the devices VLSI, WSI and GaAs technologies are ex- 
plored. The computing architectures being investigated are the 
parallel processors as the computational wave array for the on- 
line on board processor. A number of alternative solutions 
(ranging from powerful array processors as EMMA2 of Selenia to 
supercomputers having hypercube architecture) are under eva- 
luation to assess their suitability to perform final image 
understanding. Another major problem concerning these compu- 
ting architectures is the choice of a powerful software langua- 
ge for knowledge representation, rule interpretation and pro- 
blem solving strategies. 
In addition to a preliminary identification of possible 
applications for the ARTS-IP system, the simulation-applica- 
tion WG is also concerned with a better definition of the 
role, the architecture and the input/output formats of the 
ARTS-IP simulator. This is accomplished by identifying the 
project needs in terms of data sources and system testing 
and validation. A critical review of existing product and 
system simulators is being done. It is expected to have recom- 
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