0 DD DU 
Sup. * 
  
This number can be reduced by one or two orders of magnitude using 
fast convolution algorithms, which operate in the frequency domain. 
In the next section, some alternatives for providing this enor- 
mous computation power will be discussed. 
2.2. Processor alternatives 
Two possibilities are mentioned here. One approach is the use 
of the most powerful type of computer available at present, the 
so-called  "super-computer" - main frames which usually include fast 
array processors to accomplish computationally intensive tasks. They 
achieve speeds in the order of hundreds of MOPS, which qualifies them 
for real-time SAR processing. 
The drawbacks of super-computers for this kind of tasks, however, are 
significant: they are characterized by very high purchase (typically 
$ 10 million) and maintenance costs. Consequently, they can seldom be 
used economically as dedicated machines, e.g. for radar data proces- 
sing in remote ground stations. 
An alternative approach to the problem is through the use of 
dedicated VLSI-hardware. This approach is motivated by the fact that 
the (parallel) processing power achievable on a single high packing 
density chip is continuously increasing, at  ever-decreasing cost. 
Thus, it has now become feasible to map a specific algorithm to a 
multi-processor architecture, the configuration of which reflects the 
structure of the algorithm. This evolution makes the use of dedicated 
hardware processors an attractive alternative for high-throughput 
signal processing applications, as will be demonstrated in this paper 
by means of the real-time SAR-range compressor. 
2.3. Systolic-array convolver 
Array architecture. 
The architecture that has been chosen for the SAR-convolver 
belongs to the systolic designs [3,4], which provide high data 
throughput rates by making extensive use of the concurrent computing 
capacity which can be fitted on one VLSI-chip. To reduce circuit 
complexity =- and consequently design and implementation cost - they 
are built up of multiple identical processor units which are inter- 
connected in a simple, regular pattern. In the prototype processor, 
the time domain convolution algorithm has been chosen to be mapped to 
this processor pattern. It can be written as 
N-1 
y(i) = SUM x(k)*h(k-i) 
k=0 
where x(i) represent a sequence of input data, h(i) are the convolu- 
tion kernel coefficients and N is the kernel length. Although it 
induces a higher number of operations than its counterparts using 
FFT, the sums-of-products sequence it consists of features the 
simplest inherent structure and the highest repetitivity. 
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