LS 
A. 
LS 
m BD N N HS 
a 
  
The idea of the synchronous machine is to produce one azimuth compressed 
output sample per raw data input sample. (Dummy samples can substitute 
the loss caused by the matched filter length.) For the range compression 
module an architecture as proposed by Dillen and Kluge (ref. 1) can be 
chosen. 
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
SAR Host Processor 
4 
raw data coefficients image 
samples and control samples 
D" "———LI— 1 "° “sms eel ee an a = 0e mm mr a 
; i 
Input Output 
Buffer Buffer I 
| I Control ! 
| - Processor ? - ! 
| Range . Azimuth | 
| | Compression Compression | 
| Module Module | 
1 range compressed 
| data samples 1 
bic mm Tan Tr Tun Tan la d me m Diei mue ien. ciem re. 0 a imp iem mm i a Diam Mies i em em m 
Figure 2: Fast Time Domain Processor (FTDP). The Control 
Processor clock synchronizes the FTDP. With each 
sample processing cycle a new raw data sample is requested 
from the host and a SAR image sample is returned to it. 
The double arrows indicate control and data flow. 
There are various ways to implement the algorithm given by equation [5] 
with a fast dedicated hardware architecture. 
Two principal approaches for the azimuth compression module will be con- 
sidered here in more detail. Both of them have the following common 
characteristics: 
- there are as many processing elements working in parallel as range 
lines needed to cover the azimuth matched filter length, 
- each processing element has its own digital signal processing (DSP) 
chip 
and associated to it memory sufficient to store a complete range 
column. 
The azimuth compression module is the most demanding part of the SAR 
processor. The throughput rate is determined by the DSP chip selected 
and the number of machine cycles required to compute the inner sum of 
equation [5]. 
3.2 Azimuth Compression Module with Storage of Input Data 
Samples coming out from the range compression process are fed into a 
concatenated sequence of shift memories; each one can hold a complete 
range line and is associated to a processing element which performs the 
arithmetic operations. 
With every new sample all existing samples are shifted by one place. The 
sample output from shift memory k is input to shift memory k+l and 
simultaneously into processing element k (figure 3). 
This scheme is used to intermediately store all range compressed data 
avoiding corner turning operations, and to feed with each new range 
sample all samples along an azimuth line into the azimuth processing 
elements. 
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