range compressed 
input delayed by 
4 range columns 
NY 3 Eel? aur MOM MM 
range compressed 
input sample 
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
shift shift shift shift each memory 
memory memory memory memory with capa- 
city of one 
n n+l nee n+3 range column 
pro- pro- pro pro- interface to 
ces- ces- ces- ces—- p— control 
sor sor sor sor processor 
n n*1 n*e n+3 
adder 
1 
p output to next cascade level 
Figure 3: Azimuth compression module version À with input 
buffering: part with 4 processing elements. 
The processors are synchronized; uith each processing 
cycle all range compressed data are shifted by one 
place, the samples leaving the shift memories enter 
simultaneously the associated processors, and the results 
are Fed into the cascade adder. 
  
Each processing element is dedicated to a fixed position within the azi- 
muth matched filter. The constituent parts of such a processing element 
are a digital signal processing chip and two small memories: 
one used for storage of coefficients, the other one used as input buffer 
in order to manage the range cell migration offset. 
A processing element produces per input sample the accumulated factors 
expressed by the inner sum of equation 5]. This intermediate result is 
fed into a cascade adder which covers as many processing elements as 
needed for the synthetic aperture or sub-aperture length. 
Consequently, the whole azimuth compression process produces for each 
range compressed input sample simultaneously as many output samples as 
there are separated looks. This concept allows the process to run conti- 
nuously over a whole scene for which the radar geometry is almost con- 
stant. 
The interpolation and matched filter coefficients are related to the 
radar range. They will be changed at appropriate steps, e.g. every 64 
samples; the overall cycle corresponds to the length of the range 
column. 
Both, the input buffer and the coefficient memory will be organized 
cyclically in order to minimize the address computation for accessing 
these data. The monotonic vatiation of the range cell migration offset 
with range fits well into a cyclic access to data of the input buffer: 
the regular stepping can easily be incorporated into the address compu- 
tation. Hence, the whole process can be implemented in a pipelined way. 
442 
  
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