Lu uad 
  
  
  
HORIZ 
  
  
SYNC 
VERT 
  
SYNC 
  
FRAME 
SYNC 
CLOCK 
GENERATION 
  
Xi 
  
x; — MOM Rilx) 
  
  
“1 ARITH. UNIT 
  
  
  
  
y; — MOM Ri (xi) 
  
  
ARITH. UNIT 
  
  
  
Ri (x;) 
}—-| AREAiCNTR 
x CLR 
  
y CLR 
  
MOM ACC CLR 
  
  
x SCALE (x4), (%2 x¢) 
  
y SCALE (yy) 
  
  
FIELD F/F 
  
  
  
  
  
  
  
  
  
  
  
  
x; — WINDOW 
  
  
POS./SIZE 
CONTROL 
  
  
  
  
y; - WINDOW 
  
POS./SIZE 
CONTROL 
  
  
X, 
  
YEi 
  
  
  
Yt 
  
XE; 
  
  
  
SAMPLE A 
SIGNAL Y 
GATING i 
  
  
  
  
  
R,(t) »  ;tV,(t)] 
  
V; SELECT 
| 
  
  
  
  
  
  
  
  
  
FIG. 15: CONTROL SIGNAL DISTRIBUTION DIAGRAM FOR THE VIDEO 
SAMPLING PROCESSOR 
  
26 
(