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393 
Communication between processors and with memories are performed through a 
double ring bus. It has been shown in (2) and (3) that with the selected 
protocol the double ring bus provides a high throughput (20 Mbytes/s) on a 
restricted number of wires (96) and can in fact be used as a conventional 
3 state bus. Furthermore, the bus protocol ensures no waste of bus 
traffic, so that effective throughput can be equal to nominal throughput. 
Two kinds of ring bus interface modules are provided to the processor or 
memory modules (abonnees), (a) the active bus interface (ABI) allowing an 
abonnee to send, read or write orders through the bus, and (b) the passive 
bus interface (PBI) allowing an abonnee to receive and respond to read and 
write orders from the bus. 
Typically processor abonnees are interfaced through ABI's and memory 
abonnees through PBI's. Nevertheless, in some applications, including the 
present one, it may be interesting to interface processors through PBI's 
or through both ABI's and PBI's. 
Both ABI and PBI contain a RAM simulating a double port access. One part 
is for processor accesses, the other for ring bus access. Data as well as 
exchange orders are contained in these RAM's. In fact, ABI or PBI merely 
appears as RAM locations on a bus internal to the abonnee. The rings bus 
function consists in routing data from one ABI RAM to a PBI RAM or 
viceversa according to an exchange order located in the requesting ABI 
RAM. 
Two kinds of original processing abonness have been developed up to now. 
One is made out of an AMD 29116 processor associated with a 16x16 
multiplier-accumulator. The other one is a cluster of up to 8 monochip 
Texas TMS 320 processors sharing access to ABI or PBI. In the present 
application, the second solution provides more processing power for a 
smaller power consumption. 
2.1.4 SAR Processing implementation 
  
From an implementation point of view, SAR image can be divided into the 
four following steps: 
1. Input data samples are entered into a Main Corner Turning Memory 
(MCTM) range after range line in bursts. 
2. Corner turned data is azimuth processed and consists per azimuth 
line of, reference function 256 point (complex) vector 
multiplication (including window weighting), 256 point FFT, 
square modulus detection and cummulative summation of selected 
output samples (look summation). 
3. Look summed data is then entered into a Re-Corner Turning Memory 
(RCTM). 
4. Each range line of RCTM is then deskewed and output. 
Untill the deskew operation, each azimuth processing task is confined to a 
single range bin and hence, a straightforward inplementation consists in 
dividing the azimuth processing task over as many processors as necessary, 
each processor being in charge of a fraction of the total of 4500 azimuth 
processing looks. Typically, one TMS-320 processor needs 3.7 ms to 
perform 256 complex multiplications, a 256 point FFT, 256 (or less) square 
modulus computations and 256 (or less) accumulations of the results into a 
256 word array containing the cumulative sum of 4 successive tools. :