39% 
available. Since such a chip is 6 times as fast as TMS-320 for FFT 
computations a combination of 2 TMS-320's plus one FFT chip would 
favourably replace a cluster of 8 TMS-320's resulting in a 60% power 
reduction per processor cluster and a total of 100W for the azimuth 
processor. 
2.2 Flexible Hardware Approach of a Synthetic Aperture Radar Processor 
and its Technological Aspects 
A modular, realtime SAR-Processor Breadboard, based on the ESTEC SPECAN 
concept, is presently being developed by DORNIER under contract of DFVLR 
and funded by the German Ministry of Research and Technology (BMFT) (5). 
The digital ground processor resulting from these activities shall be able 
to produce two-dimensional SAR images taking raw radar data of the German 
X-band radar system MRSE (Microwave Remote Sensing Experiment) as well as 
the C-band ESA-ERS 1 system. Additionally, further adaptability of the 
processor to spaceborne/airborne SAR-systems shall be possible. 
The basic features of the processor are given by the image specification 
listed in Table 2 which are regarded to be a common baseline for earth 
exploration purposes within ESA (European Space Agency) and DFVLR (German 
Authority for Aerospace Research). Furthermore, the processor concept is 
strongly influenced by a high throughput demand (realtime processing) at 
low power consumption rates in order to allow for a future upgrading of 
the processor to spaceborne/airborne applications. 
Finally, a high modularity and, if possible, repeatability of functional 
groups within the processor is required for reasons of cost reduction and 
simple maintainability. 
22.4 Processor Architecture 
  
The architecture of the SAR-Processor Breadboard is shown in Fig. 2-1. It 
consists of a high speed radar data processing pipeline including the 
hardware modules. 
^ Reference Function 
- Corner Turn Memory (CTM) 
- Fourier Transformation (FFT) 
- Look Summation (LS) 
- Radiometric Correction (RC) 
- Azimuth Deskew  (AZD) 
-  Recorner Turn Memory (RCTM) 
-  Deskew (DSK) 
which performs the azimuth compression, look summation and post-processing 
of 1024 range samples (appr. 20 km swathwidth) at an input data rate of 
up to 3 MHz. Identical hardware pipelines are paralleled if a full swath 
must be processed in realtime. In this case, two additional models 
-  Subswath formation (at the input) 
- Full Swath formation (at the output) 
are required for a complete processor (see Fig. 2-2). 
Each fast processing pipeline is controlled by three medium speed control 
modules whic provide for the parameters required by the pipeline modules. 
At this control level control data must be computed at a rate of typically