396 
  
  
  
397 
2-10 K words/sec depending on the module and the SAR-sensor itself. 
Finally, a slow speed P-Controller forms the processor interface to the 
external environment, 
Range compression and Linear Range Migration Correction are performed in 
front of the Azimuth Processor in a SAW device and by proper sampling 
control of the AD-converter (see Fig. 2-2), respectively. 
2.2.3 Implementation of the processor 
The implementation of the processor is accomplished under the aspect that 
each specifically designed hardware module must include enough commonality 
and flexibility to make it a part of a more general signal processing 
hardware family. This concept allows the functional modules to be used at 
several places of the processor (e.g. see Storage Unit) or even supports 
the implementation of different image processing tasks (e.g. other 
SAR-algorithms, pattern recognition etc.) at low development cost using 
the same hardware modules in different arrangements. Fig. 3-1 shows a 
block diagram of the signal processing hardware family. 
Some of the more important modules of the SAR-Processor Breadboard are 
described in more detail in the subsections below. 
2.2.3.1 High Speed Storage Unit 
Intermediate storage of the data frames is one of the most important 
functions of any kind of image processing. In a SAR-processor those 
memory units are used during Corner Turning, Look Summation, Recorner 
Turning, video display storage and test pattern generation. In order to 
cover these applications a universal memory board has been developed which 
allows for writing and reading line based image data in both range and 
azimuth direction. The length of each line can be programmed within the 
total capacity of 256 Kwords, where the word length can be any value up to 
16 bits. 
The memory boards can easily be cascaded if more than 256 Kwords of memory 
size is required. 
Dynamic NMOS memory chips (64 k 1) and TTL-ALS contro! circuits are used 
for the board, the size of which is 233x160 mm’. A write/read speed of up 
to 3 Mwords/sec could be achieved at a power consumption of 3.2 Watt. 
Refresh circuits for the dynamic memory chips are included on the board. 
A complete memory system (e.g. CTM) is built up of 3 memory boards and a 
simple controller board which provides for the correct input/output 
interface some trigger signals which tell the memory boards to write/read 
frames. The total power consumption of the CTM has been measured to be 
13.5 Watt; ; 
272.3.2: Finite Impulse Response Filter 
FIR filters are widely used for low pass filtering, bandpass filtring (in 
combination with a complex premultiplication), digital interpolation and 
correlation. In a SAR-processor, digital interpolation/resampling is 
required for the postprocessing module.