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A two-channel FIR filter offering programmable length of up to 256 samples
at a word length of 16 bit (data and coefficients each) has been developed
using a TRW multiplier/accumulator circuit and TLL-ALS control logic on a
standard 233x160 mm^ board. Subsampling of the output signal is possible
if the FIR filter is used as a lowpass filter.
The maximum input data rate is given by the internal 12 MHz computation
clock, the filter length and the chosen subsampling factor. At a filter
length of 16 (no subsampling), the input rate can be up to 0.72
Mwords/sec. The power consumption is 9.1 Watt.
The filter coefficients are stored in a 2Kx8 PROM offering a large variety
of different, selectable coefficient sets.
2.2.3.3 Complex Multiplication
A complex multiplication module has been developed on the basis of a fast
TRW multiplier and some TTL-ALS control logic. The whole circuit is
implemented on a board of the size 160x100 mm . It can operate up to an
input data rate of 3 Mwords/sec. The power consumption turned out to be
3.0 Watt including output rounding and saturation limitation circuits.
Data word length can be up to 16 bit at both input and output.
This unit is used as the Reference Function Multiplication module of the
SAR-Processor. Additionally, detection and radiometric correction can be
performed with minor changes of the hardware.
2.2.3.4 Fast Fourier Transformation (FFT)
A hardware FFT module is presently under design at DORNIER. It is based
on the Radix 2 Decimation-in-Time algorithm showing the following
features:
- complex input up to 16I, 160
- complex output up to 16I, 16Q
- Programmable FFT length of 32-64-128-256-512-1024-2048-4096
- complex butterfly hardware element, operating at approx. 15 MHz
- FFT data addressing scheme downloaded from external device.
This module will be able to perform the operations required for azimuth/
range compression of the SPECAN method as well as of the frequency domain
algorithm. ;
2.2.3.5 Medium Speed Pipeline Controllers
The pipeline controllers of the SAR-Processor Breadboard convert the more
general control parameters (e.g. Mean Doppler Frequency, FM-Rate, Antenna
pointing angles) into secondary control parameters which are used by the
pipeline modules. The basic arithmic operations are required in order to
perform these transformations. Since the output data rates are around
2-10 Kwords/sec, a signal processor like the NEC 7720 is a favorite
candidate for these jobs.
The EPROM version NEC 77P20 allows for a flexible programming of both the
instructions ROM and data ROM.