398 
  
  
  
399 
2.2.4 Adaptation to on-board processing 
On-board applications of the flexible hardware concept are characterized 
by stronger requirements with respect to 
- electrical power consumption 
- weight and volume 
- reliability 
For the Breadboard described the power consumption of a complete subswath 
processing pipeline (1024 range samples) including the pipeline 
controllers amounts to 85 Watt approximately. These circuits are located 
on 17 boards each of the size 233x160 mm at a height of 14 mm. 
Therefore, the active volume of the boards equals 8.8 liter at a total 
weight of 6 kg. : 
For an on-board SAR processor both power consumption and weight/volume 
could be reduced by 
- use of high speed CMOS circuits 
- Use of chip carrier packages (i.s.o0. IC sockets as for the 
Breadboard : 
- custom designed circuits for repetitive elements within the 
processor 
- smaller connectors 
- compressed layout of boards 
Taking a pessimistic estimate of the improvements caused by the above 
measures a reduction by a factor of two for both power consumption and 
weight should be achievable. 
Thus, typical figures for each on-board subswath processor would be: 
40 Watt 
3.5 kg 
power consumption 
weight (incl. frame) 
The number of pipelines necessary for a full swath processor will be in 
the order of five. Additionally, more pipelines might be required due to 
reliability reasons. No reliability computations have been performed up 
to now for the on-board version of the processor. 
The above budget of weight/volume and power consumption is not complete. 
Contributions of the Mean Doppler Tracker, FM-Tracker and the interface 
circuits to telemetry must be added. 
CONCLUSION 
The two different processing implementations analysed show that with 
to-day's technology an azimuth processor can be constructed consuming 
about 200W and weighting 20 to 25 kg. From the description of the 
architectures presented it is concluded that: 
= The HSPP Concept uses standard bus interfaces and a standard bus 
protocol, which allows to implement at relative low cost 
multiprocessor architectures for a specific signal processing task. 
The processor performance is kept up to date by incorporating the 
latest available VLSI processing chips (DSP's or FFT chips). For 
example when the announced C-MOS versions of the TMS-320 DSP are used