400 
for the azimuth processing PR CN the power consumption will be 
reduced to about 100W. 
- The flexible hardware concept uses task dedicated standard modules 
belonging to a signal processing hardware family. Task dedication 
permits to save hardware as compared to more general purpose 
programmable DSP's and therefore potentially this approach leads to 
minimum power and weight architectures in combination with (semi) 
-custom VLSI technology. 
However the relatively high cost related to VLSI (semi)-custom design and 
the construction and testing of task dedicated multi module parallel 
pipeline architectures and their control hardware may be prohibitive in 
exploiting fully its potential saving. 
Hence each of the described architectures has its own (time evolving) 
specific merits which will determine the selection of its use for a 
specific application. 
ACKNOWLEDGMENT 
We would like to express our thanks to Mr. J. Larcher and Mr. Nguyen for 
their contributions to the MATRA SAR processor application study. 
REFERENCES 
(1) De Gavre J.C., Okkes R., Gaillat G., "Study of a programmable high 
speed processor for use on-board satellites". 
4th Symposium on Computers in Aerospace, Hartford 1983. 
(2) Gaillat G., "The design of a parallel processor for image processing 
on-board satellite: An application oriented approach”. 
10th Annual Symposium on Computer Architecture, Stockholm 1983. 
(3) Matra, "HSPP architecture report". 
Matra Internal report EPT/063/339/83, 1983. 
(4) Covert G.D., "A 32 point monolithic FFT processor chip". 
International Conference on Acoustic, Speech and Signal processing, 
Paris 1982. 
(5) R. Schotter, "Real-time SAR Processor", 
1982 International Geoscience and Remote Sensing Symposium (IGARSS 
1982). 
(6) Bennet J.R. et al, "Algorithms for pre-processing of satellite SAR 
data". 
ISPRS Commission II Symposium, Ottawa 1982