422 
Fig. 1 
(a) Experimental digital processing 
system showing CCD camera, 
electronics and output monitor. 
  
  
(b) Main sections of Fig. l(a). 
  
  
  
   
   
  
  
  
  
  
  
  
  
  
  
  
  
   
  
  
  
  
[memo mmm oo m 4 
1 1 
P VIDEO X FRAME- ; WHOLE-FRAME 
CAMERA bad GRAB : DISPLAYS 
AN Di Dd MEMORY : PROCESSOR 
| = STORE ON COMMAND 
t : 
i 1 
SUB-FRAME | 
- (WINDOW) ! — DECISION 
d. 
(Correlation 
Convolution) 
IMAGE -—— PROCESSOR — | OUTPUT 
CAPTURE ADDRESS 
  
  
       
COP DATA COEFFICIENT 
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
        
         
      
     
     
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
ENTRY AND Processed Image Data 
SCANNER MEMORY acis = 
= f mme 
: | PUSOATEC FOISPLAY [^ 
FRAME LINE MULTIPLIER- ALU ay OF GB EMORT pm S 
CCD GRAB MEMORY ACCUMULATOR LOGIC I ET TT D | 
| E 4 
CAMERA MEMORY|,.., — ss qe | tee ATS 
: + 7 
+ nn ICOEFÉ, 
X17 ; Address aie | |» DIGITAL OUTPUT —#TRANSMIT, 
: STORE 
TIMING ’ MULT.- ACC. 
— à Li MES 
COMPUTER-----4 AND : LINE MEM #2 
conto : CORR: CONTROL 
/ N : PROC. SIGNALS 
TESTE A 
| 
N -8IT LONG 
ADDRESS FAST A RS G MULT i 
Sel WINDOW y CORRELATOR cc 
CORRELATOR eiecti lat MEMORY t= ; i ACC. 9% ( ) 
manie d -- X.y,Z 
CONVOLVER Bis a second 1 Y [A € 
-———— L.. iamaege oris .. : CORR. 
image Sliding ,] ADDRESS 'A' shifted. WEIGHTS 
Parameters | CONTROL NN D B 
D^ Vs 
  
  
  
  
  
Fig. 2 Electronic functions of the system, Fig. 1l. 
A/D, D/A analog to digital converter and reverse; Ml-input monitor, 
MO-output monitor, MC-correlator monitor, ALU arithmetic logic unit. 
Update or double buffer (D.B.) logic and display memory are not in 
Fig. l. n x n is implemented as 3 x 3 ; N as 64 (see text). MO may be 
a standard TV monitor or X, Y raster - driven display for nonstandard 
frame sizes and rates, depending upon the applícation.