which solved these problems.The hardware 
dependency was reduced and made 
multiusable, highspeed processing was realized. 
2. Hardware formatter 
Fig.1 Shows the block diagram of MOS-1 
MESSR formatter as a typical example of 
synchronizer. The figure shows that the 
important processing parts such as 
synchronization of minor frame, 
synchronization of major frame and serial to 
parallel conversion,are done by hardware. It is 
not only in case of MOS-1 MESSR formatter 
system, but also in the other sensor formatters. 
Each formatter hardware are not so different 
from others. But there is no interchangeability 
between each formatter at all. It is because we 
designed speed priority to cope with a large 
quantity of data .In each system, hardware are 
customized to realize high speed processing 
T o 
W orkstation 
  
DATA /CLOCK 
Inputs [7 Tm 
  
Serial/Parerel 
Converter 
LEVELO Processing 
  
Signal D river 
  
  
  
  
  
V 
SYNC 
D etectoer 
  
M NES pattern 
G enerator 
  
  
  
  
  
se 
Scram ble 
Decoder 
  
  
Status Singnal 
Input EL > 
  
Formatter status Ë 
Controller 
  
  
  
  
  
  
  
  
  
| 
  
  
  
Serial/Pararel 
Converter 
Syne. Detector 
  
  
  
  
ir 
  
  
  
Line SY NC pattern 
Generator 
  
Fig.1 : Block diagram of MOS-1 MESSR hardware synchronizer. 
3. Investigation of downlink data format of 
earth observation satellite 
Fig.2 Shows the downlink data format of 
MOS-1 MESSR/VTIR and Fig.3 Shows the 
downlink data format of JERS-1 OPS as typical 
examples. 
208 
Through for our investigation of many satellite 
downlink data format we have found that the 
way to specify recording start location of sensor 
data from minor frame sync pattern is 
same.*(1),*(2) 
If we make a circuit which is able to take 
International Archives of Photogrammetry and Remote Sensing. Vol. XXXI, Part B1. Vienna 1996