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Figure 2. A Block Diagram of the PC Interface Card 
After the input stream is converted into a parallel word 
and stored in the internal memory of a FIFO device, this 
parallel word needs to be read by a PC. This procedure 
can be done using built-in I/O routines. Using such 
routines, a microprocessor of a PC will check and read 
its I/O port specified by address. In order to assign an 
appropriate address to the FIFO memories of the PC 
interface card, an address decoding circuit should be 
designed. In this paper, a simple address decoding 
circuit was used (Chun, 1992) using a 74138 decoder. 
The selected address for the interface card is as follows. 
Table 3. Selected addresses for the interface card 
  
  
  
  
  
  
  
address Meaning 
330H 16 bits data input 
332H 8 bits data input 
333H 8 bits flag input 
334H 16 bits flag input 
  
  
As shown above and in figure 2, there are two paths of 
input stream. One path has two input streams and 16-bit 
output words. The other path has one input stream and 
8-bit output words. In case of 16-bit output, two FIFO 
devices are used for serial-to-parallel conversion and 
output from each FIFO are combined to create 16-bit 
parallel word. In case of 8-bit output, | and Q channels 
are assumed to be combined within the KITSAT-3 
receiver. 
The basic I/O routines of a PC are done using 8-bit word. 
In order to control I/O port of a PC in 16 bits, the "-IO CS 
16" pin of a PC's interface slot should be controlled 
carefully (Eggebrecht, 1992). 
Table 3 shows that two addresses are allocated to read 
flags of FIFOs. Flags indicate the status of the internal 
memory of a FIFO. By reading these, it is possible to know 
whether the FIFO's memory is full, empty, half, etc.. In the 
software to derive the PC interface card, these two 
addresses are read continuously. When half of FIFO's 
internal memories are full, the microprocessor will. read 
out parallel words stored in the memory. 
Figure 2 shows that there is an internal clock generator in 
the PC interface card. This is to prepare the situation 
where the KITSAT-3 receiver fails to provide an accurate 
clock signal. The switch between internal and external 
clock can be implemented using software but a physical 
switch is used for the current implementation. 
After the incoming bit stream passes the PC interface 
card, they are converted into parallel words and stored in 
the hard disk of a PC. Then, they undergo the frame 
synchronization process. The next subsection will 
describe the frame synchronization software. 
3.2 Frame synchronization 
The data stored into the hard disk of a PC contains not 
only image data but also auxiliary data such as telemetry 
data and header/footer. Moreover, the data stored in the 
hard disk may contain some dummy signals before frame 
header and/or after frame footer. Therefore it is important 
to identify the location of frame header and extract the 
meaningful content from a frame. This procedure is called 
Frame synchronization. 
87 
International Archives of Photogrammetry and Remote Sensing. Vol. XXXI, Part B1. Vienna 1996