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In Figure 4, data points À and B are read from memory MEM by reader R, and 
are transmitted via data bus to finally reach the modules through ring 
interface RIF. 
After beeing manipulated by the modules, the result is written in memory MEM 
by writer W. 
This method requires numerous modules. Furthermore, this method increases 
poth the amount of data transfered by data bus between modules as well as 
the amount of time that the data bus is occupied. 
In addition, the amount of time that the reader and writer are occupied is 
increased because a great number of memory input/output operations is 
necessary. 
Accordingly, it is difficult to make full use of all the capabilities of an 
overly great number of modules. 
The abovementioned fact also occurs in complex number addition and 
subtraction when using modules for real number addition and subtraction 
(Figure 5, Figure 6). 
3, COMPLEX NUMBER MODULE 
Generally, it is necessary for high speed SAR data processing to execute 
complex number operations like FFT at a high speed, however, the operations 
may be done with relatively low accuracy. 
The complex number module was conceived as follows. 
The data bus signal containing a complex number has both a real component 
and an imaginary component. In operation, the complex number module 
receives the signal, separates components and executes the complex 
operation. 
(1) DATA FORMAT FOR THE COMPLEX NUMBER MODULE 
  
A data bus signal consists of a module select flag (MSF), an identification 
segment (ID) and a data segment (DA) as shown in Figure 7. 
DA contains: the exponent (E), the real component (R) an imaginary 
component (I) of the complex number. The exponent is common to both the 
real and the imaginary components. 
(2) THE COMPLEX NUMBER MULTIPLICATION OPERATION MODULE (CNMM) 
CNMM consists of a queuing circuit and a complex multiplication circuit as 
shown in Figure 8. The complex multiplication circuit has a control 
circuit, several multipliers, an adder, and a subtractor. The circuits are 
so organized as to execute complex number multiplication in the most 
effective manner possible. 
The operation is shown in Figure 2. 
The queuing circuit is a circuit which holds a number until it's partner is 
available in dyadic operations like multiplication. 
The behavior and timing of the multipliers, adder and subtractor are shown 
in the data-flow graph in Figure 2. 
The control unit controls each operator. 
The output data from the subtractor and the adder are respectively the real 
and the imaginary components resulting from the complex multiplication. 
The results are serially transferred to the queuing circuit under control 
signals from the control circuit where a new ID and a new MSF are attached. 
Afterward, this final result is transmitted through a bus interface. 
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