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An Experimental Real-Time Processor for ERS-1 Sar Data 
J.Cl. Degavre, 
European Space Research and Technology Centre, 
Noordwijk, The Netherlands 
1. INTRODUCTION 
The C-band Real time Sar Processor Breadboard (see Figure 1) (Reference 1) 
delivered in 1984 to the European Space Research and Technology Centre 
(ESTEC) by the firms MDA and DORNIER was constituted of the minimum amount 
of hardware required to prove the concept of real-time Sar signal 
processing. 
The functions that are part of an operational real-time processor but were 
not found critical to its feasibility had been omitted. For example, the 
breadboard did not provide: 
- the interface to the real-time input signal (the output data is buffered 
at low speed from a 1600 bpi, 45 ips computer compatible taperecorder, 
then processed at real-time speed in burst); 
- the range compression; 
- the mean doppler and doppler rate (autofocus) tracking; 
- the post processor module responsible for correcting geometric 
distortions (azimuth shear and range skew) and for rearranging the 
output data in range line after azimuth processing. 
However, the control system of the breadboard was designed and implemented 
to control a complete processor pipe-line, including the tracking and post- 
processing modules. It was therefore possible without major redesign of 
the existing hardware and software to up-grade the Sar Processor Breadboard 
towards a complete Sar Processor able of delivering high quality images. 
The upgrading of the Sar Processor Breadboard, started in 1985, will result 
in an installation capable of processing at every high throughput ERS-1 
radar data (available in 1989). 
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
Figure 1 
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