| 
cycle stage 1 | stage 2 | Stage 3 (result) 
| | 
1 yl) <== 0 * XA *hy | undefined lundet ined 
(4) == | (% Bp . 
2 y, « * x, *h, | vi <a y(o« x,*hy jundefined 
3 yl4) <== 0 + x, *h | (9) <== (4) * | ez y l 
f ENTE yh EPR Vi 
Woes | u | 
4 ya/<== 0 + x, *h à) <== yl) x + Q)c== 
í y "3 i Ye Xu he i3 « yd: x 
BS. | | 
i-2 Y «az ( + X *hy | . | ... 
i-l À () --- (4 + ° * | 
| y y^ xi À id 
| | 
1 .. oe 6) «-- o), ‚*h 
| p wt 
| | 
| | 
Table 2. Computation schedule of systolic convolver 
  
  
  
The inherent structure of the pipeline makes the use of any 
special control logic or bus structures superfluous. The (interme- 
diate) results flow naturally from one processor stage into the next, 
where each time they "meet" the appropriate data sample and  coeffi- 
cient. The different stages merely have to be synchronized by a 
master pipeline clock, which is wired in parallel to each pipeline 
register (see below - cell description). In the case of the convol- 
ver, where the filter coefficients are stored in read/write registers 
in order to allow for different filter functions, one additional 
signal (load clock) has to be provided which controls the loading of 
these registers. 
Cell description. 
Fig. 2 ‚contains. the logic diagram of one processor element. 
Input data are wired to one input of a binary multiplier. The 
other multiplicand is provided by the coefficient register (CR). The 
product is fed to an adder, which accumulates it to the intermediate 
result delivered by the previous stage. The sum is stored in the 
pipeline register (PR) by the master pipeline clock. 
The CR can be loaded with the current contents of the previous pipe- 
line element under control of the load clock. In this way, one can 
shift a filter kernel sequence into the pipeline and then store it in 
the CR's with one load clock pulse. 
The path widths of the different signals are as follows: 
x, - 5 bits 
h : 6 bits 
ys 120 pits 
t 
405