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A COMPRESSION FILTER FOR REAL-TIME SYNTHETIC 
APERTURE RADAR (SAR) DATA 
W. Dillen 
G. Kluge 
European Space Agency - Operations centre (ESOC) 
Robert Bosch-Strasse 5 
D-6100 DARMSTADT 
Federal Republic of Germany 
0. Abstract 
A high-throughput hardware processor is presented which performs 
real-time range compression of SAR-data. It is based on a "systolic 
array" architecture which computes the convolution algorithm without 
using Fourier transforms. 
A prototype of this machine has been built in semi-custom CMOS gate 
array IC's. Full advantage is taken of the regularity and repetitivi- 
ty which is inherent to the architecture. Each chip implements a 
(real) convolution of twelve kernel coefficients which results in an 
arithmetic rate of 120 million operations per second (MOPS) when 
operated at 5 MHz. At this speed, the SAR-range processor as a whole, 
which contains 240 gate arrays to realise a 720-point complex convo- 
lution, achieves 28.8 GOPS. 
The price of one gate array chip being approximately $ 200, the cost 
of arithmetic operations is under $ 2 per MOPS. This example shows 
that special-purpose systolic arrays, based on commercially available 
integrated circuits, can offer arithmetic processing power several 
orders of magnitude cheaper than programmable array processors or so- 
called supercomputers. 
1. Introduction 
Initially, the processing of SAR-data has been carried out by 
analog computers, using optical methods. They had the advantage of 
basically instantaneously accomplishing data compression in both 
range and azimuth direction [1]. However, the drawbacks of analog 
machines compared to digital processors - lack of flexibility, sensi- 
tivity to noise, temperature changes, aging, etc. - became more 
significant as the latter grew faster and more powerful. 
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